This invention generally relates to microprocessor and integrated circuit design techniques and specifically relates to the characterization of the noise sensitivity of integrated circuits.
Signal noise, line loading, and line coupling all contribute to signal degradation and cause much concern in the design and production of high speed Very Large Scale Integrated (VLSI) circuits. The effects of these phenomena are especially troublesome in the design of circuitry comprising numerous closely packed signal lines and densely packed logic circuits. To achieve minimum size and maximum design of integrated circuits involves a lengthy phase of design optimization followed by multiple design iteration. During design validation, a database representing the proposed integrated circuit is used to model the proposed silicon integrated circuit as closely as possible before a prototype or production integrated circuit is manufactured. The model of the integrated circuit is used to test and verify performance of the design and to identify and avoid potential and actual problems and the issues which are expected to occur once the integrated circuit is manufactured.
In accordance with Moore""s law, miniaturization of the integrated circuits and the wires which connect the various transistors on an integrated circuit must support the doubling of circuit density every 18 months. State of the art processors utilizing 0.18 micron and smaller feature sizes, cramming tens-of-millions of transistors on a single die have between six and eight layers of metal used for wires interconnecting the underlying logic and transistors. In an effort to reduce the resistance associated with these wires, the width of the wires has been decreased to maintain compatibility with ever decreasing feature sizes, while the individual wires have grown in height. This reduced resistance allows an increase in connecting speed between transistors. However, these modifications in the width and height of the wires also affect interferences associated with neighboring wires.
In densely packed 0.18 micron and smaller integrated circuits, the capacitance effects between neighboring wires is difficult to accurately predict. Capacitance effects between wires can be impacted by a change in the direction of current in neighboring wires, the amount of current in neighboring wires, and the accumulative effects of neighboring wires within a specific distance. This interference is the result of the parasitic capacitance which is a product of the electric field between wires. This static electric field is caused by a voltage potential between two conductors when an insulator is located between the two conductors, resulting in capacitor coupling of the wires.
Capacitance loading can also have an adverse effect on signals carried on wires which were intended to maintain a constant voltage. The capacitance loading will effectively superimpose an additional current on the wire that is required to maintain the constant voltage and may result in a voltage spike which must be absorbed by the components (e.g., signal driver or signal receiver) connected to this wire. These voltage spikes may result in circuit failures. A wire in a VLSI circuit is usually viewed as having a driving circuit (a driver), the wire, and one or more receiving circuit (a receiver). If these voltage spikes reach the receivers connected to the effected or victim wire, which are required to maintain a constant voltage, the receiver may switch states within the dense wire environment of an integrated circuit resulting in a circuit failure.
If these loading effects are identified early, they may be prevented by spacing the wires further apart, increasing the driver strength (e.g., current driving capacity) or by making the receiver less sensitive to a voltage spike. Sensitivity to noise or noise problems are typically identified by the receiver""s response to the voltage spike. If the receiver ignores the voltage spike the noise problem may be ignored, because it does not cause a malfunction in the integrated circuit. However, if the voltage spike causes an adverse reaction in the receiver, the interference is at such a level that it must be resolved.
Systems and methods for investigating electrical characteristics of a multi-level interstructure are known. Such systems use complicated algorithms for simulating a circuit. The process is complicated by the fact that adjacent interconnects, or wires, sometimes follow non-parallel paths. Another complexity is that there is a non-linear relationship between some process variables and electrical characteristics. For example, the relationship between capacitance and the space between adjacent interconnects, or wires, is non-linear. Consequently, the computation and simulation procedures are complex and are typically performed using Electrical Design Automation (EDA) tools. For example, HIVE is a software package that performs 2D numerical field simulations for interconnects having given geometries to arrive at the closest-fit analytical functions. As another example, Simulation Program with Integrated Circuit Emphasis (SPICE) is a software package that is commercially available for simulating inter alia electrical performance of complex Very Large Scale Integrated (VLSI) chips. SPICE requires inputs in the form of a SPICE subcircuit datafile, known in the art as a xe2x80x9cSPICE deckxe2x80x9d which numerically characterizes and describes the value and type of every conductor and component of the VLSI chip.
Many common computer simulators are also variations of the simulator tool SPICE. These programs typically operate by accepting circuit frequency response parameters, either directly from a Computer Aided Design (CAD) package, a simulator (using discrete frequencies to directly measure frequency response of a circuit prototype) or other means. Based upon these parameters, the simulator is then typically used to, simulate special signal conditions for the circuit which are usually not discrete frequencies, i.e., to predict transit responses in an integrated circuit. The computer based simulator typically use numbers which represent test input signals, e.g., initial voltages, currents and frequencies. The simulators are then usually used to conduct a time based analysis of responses to the input signal conditions of the different measurement points of the circuit. These tools can be used to determine the noise characteristics and sensitivity of circuit designs.
While numerous SPICE simulations can accurately simulate the operation of the integrated circuit, the required number of SPICE simulations is expensive both financially and computationally. The SPICE simulator accurately simulates wires and circuits with respect to their voltage and current behavior. However, in order to identify potential noise problems on an integrated circuit, numerous SPICE simulations must be performed. In these numerous SPICE simulations, variables such as the switching speed of neighboring wires, the distance between the aggressor wire and the victim wire, the length of the victim wire which runs parallel to the aggressor wire, the strength of the driver, and the sensitivity of the receiver must all be known and possibly varied to adequately investigate the potential noise problem. To accurately determine the extent of the noise problem in a typical LSI or VLSI circuit literally millions of SPICE iterations would need to be performed. Normally, simplifying assumptions are made to reduce the number of SPICE iterations which must be performed. These simplifying assumptions may impose restrictions upon the design itself. For example, restrictions may be imposed on wire spacing, the number of stages of inverters used to reject voltage spikes in receivers, the shielding required to reduce or eliminate line capacitance, and other such integrated circuit design limitations may be imposed. These limitations may result in a less than optimal design.
A need exists for a system and methodology that will analyze integrated circuits with xe2x80x9cSPICE-likexe2x80x9d accuracy at a fraction of the cost and computational intensity required by SPICE or similar full-featured circuit simulator. A further need exists for the identification of interference determining parameters or criteria that can be used to classify receivers within an integrated circuit as either being susceptible to noise interference or predicted to be operating within their design limitations.
This need and other features and technical advantages are achieved by a method of designing an integrated circuit which includes the steps of determining a layout of components of the integrated circuit and identifying noise susceptibility factors for pairs of the coupled components included in the layout. These noise susceptibility factors are then used to access predetermined noise characteristics to predict the noise characteristics of the integrated circuit. The step of identifying pairs of the components may further include the steps of identifying a driver, a receiver, and an interconnection therebetween. The step of identifying noise susceptibility factors may include the steps of determining a percent of xe2x80x9cbadxe2x80x9d capacitance to total capacitance of wire coupling the pairs of components; and determining the noise characteristics using the percent of capacitance. The step of identifying noise susceptibility factors may include the steps of calculating a total length of each corresponding wire coupling the pairs of components that are subject to capacitive coupling; and determining respective noise characteristics using each of the total lengths. The step of identifying noise susceptibility factors may include the steps of calculating a driver output impedance of driving circuits, where each driving circuit comprising one of the components of each of the pair of coupled components; and determining the noise characteristics using the respective driver output impedances. The step of identifying noise susceptibility factors may include the steps of determining a percentage of bad capacitance to total capacitance of a wire connecting the pairs of components; calculating a total length of each of corresponding wires coupling said pairs of components; calculating a driver output impedance of driving circuits each comprising one of the components of each of the pair of coupled components; and determining respective noise characteristic using the percentage of a bad capacitance to total capacitance, the effective total length of wire and the driver output impedance. The step of generating the prestored noise characteristics as a function of the noise susceptibility factors may also be included.
Another embodiment of the invention includes a tool for the design of an integrated circuits which includes an integrated circuit layout tool providing an integrated circuit layout which includes a plurality of pairs of coupled components where each pair is coupled by a respective wire. The tool may also include a noise calculation tool which provides noise susceptibility factors for each of the coupled components in the circuit layout; and a noise calculation tool which provides parameter noise characteristics of each of the wires using a prestored value retrieved as a function of the noise susceptibility factors. The integrated circuit layout tool may include semiconductor devices. The noise calculation tool may include the percent of a bad capacitance to total capacitance of a wire coupling the pairs of components. The noise calculation tool may include an effective total length of each of corresponding wires coupling the pairs of components that are subject to parasitic capacitance. The noise calculation tool may also include a driver output impedance of driving circuits each comprising one of the components of each of the pairs of coupled components and the percent of capacitance of wire coupling the pair of components. The noise calculation tool may also include an effective total length of each of corresponding wires coupling the pairs of components that are subject to parasitic capacitance and a driver output impedance of driving circuits each comprising one of the components of each of the pair of coupled components.
Another embodiment of the present invention includes an integrated circuit formed by the steps of specifying a layout of components included in the integrated circuit in which coupled pairs of the components are identified and noise susceptibility factors for the pairs of coupled components is also identified. The noise susceptibility factors may be used to retrieve prestored noise characteristics. The pairs of coupled components may further include a driver, a receiver, and an interconnection between the two. The noise susceptibility factors may include the percent of bad capacitance to total capacitance of a wire coupling the pairs of components, and an effective total length of each of corresponding wires coupling the pairs of components that are subject to bad capacitance coupling. The noise susceptibility factors may further include a driver output impedance of driving circuits each comprising one of the components of each of the pair of coupling components,
It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.